Gate array architecture and layout for deep space applications
US5543736A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.