Compact page-erasable eeprom non-volatile memory
US5544103A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 1994 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Jul 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism. In this embodiment, the second layer preferably comprises a word line or row of a memory array. The erasure from the first layer (floating gate) to the second layer (word line) facilitates the providing of a compact, page-alterable non-volatile memory array. In …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.