Apparatus for caching smram in an intel processor based computer system employing system management mode
US5544344A · kind A · utility
17Cited by
2References
18Claims
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Key dates
| Filing date | Dec 6, 1994 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Dec 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an SMRAM status bit corresponding to each data entry. The SMRAM status bit is set if the data entry holds data in SMRAM, and reset if the data entry does not hold data in SMRAM. The SMRAM status bit distinguishes SMRAM data from system memory data in the cache, thereby eliminating cache coherency problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.