NAPNOP circuit for conserving power in computer systems
US5546037A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1993 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Nov 15, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.