Phase locked loop circuit with phase/frequency detector which eliminates dead zones
US5546052A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.