Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted
US5546410A · kind A · utility
19Cited by
7References
4Claims
0Family size
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Key dates
| Filing date | Aug 2, 1994 |
| Grant date | Aug 13, 1996 |
| Priority date | — |
| Expiry date | Aug 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a built-in error correction system for correcting undesirably inverted data bits, and the built-in error correction system starts a parity bit generating sequence and an error correcting sequence only when increase of error rate is forecasted, thereby increasing the access speed without sacrifice of the reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.