Semiconductor device with reduced tunnel resistance and circuitry using the same
US5548138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1993 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Sep 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/801
Abstract
In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.