Field effect transistor
US5548150A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/901
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.