Circuit arrangement for driving a MOS field-effect transistor
US5548240A · kind A · utility
Inventor
Key dates
| Filing date | Mar 1, 1995 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Mar 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for gate-controlling a MOS field-effect transistor (T.sub.o) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C.sub.GS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U.sub.GS) has dropped below a predetermined limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.