Method and apparatus for providing high-speed column redundancy
US5548553A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.