Asynchronous transfer mode adapter for desktop applications
US5548587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Sep 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An ATM adapter for desktop applications includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of an interrupt circuit that goes to the SBus as well as a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit. The physical interface circuit also receives formatted ATM information and sends that information to the reassembly engine. The reassembly engine reassembles the ATM data and transmits it through the RAM interface/arbiter circuit to the RAM bus. F…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.