Method and apparatus for fault tolerant fast writes through buffer dumping
US5548711A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails. A backup power source is provided to ensure that power will be available to at least one of the two memories such that the data that has been received within the controller will always be accessible. Accordingly, since the data will be accessible, even if of a failure of any single component or power…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.