Multi-processor data processing system having multiple ports coupled to multiple interface circuits
US5548771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1993 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Nov 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor data processing system (10) includes an array (12) of one or more data processors (50-65). Data processing system (10) has edge interface circuits (14,16) for transferring control and data to and from the array (12). A data bus (32), an address bus (34), and a control bus (36) each transfers information to and from the array (12), the edge interfaces (14,16), and a bus interface controller (22). In an alternate embodiment, multi-processor data processing system (210) includes an array (212) of one or more data processors (250-258). Data processing system (210) has edge interfaces (214-217) for transferring control and data to and from the array (212). A data bus (232), an address bus (234), and a control bus (236) each transfers information to and from the array (212), the edge interfaces (214-217), and a bus interface controller (222).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.