Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to receiving units when ready
US5548785A · kind A · utility
20Cited by
17References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1993 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Jul 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.