Input/output control system with plural channel paths to I/O devices
US5548791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Jul 25, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a host processor and host memory means. The processor interacts with a plurality of peripheral units through an I/O system that includes a plurality of channels, one or more I/O processors (IOP's), and control data in a system area of the host memory means. Each channel has an associated busy bit in a vector, and is provided with a one position queue for dispatching work to the channel. Each queue has a bit in a vector indicating its full or empty status. A very efficient algorithm for the assignment of work for peripherals by the IOP's is provided in a system that provides for multiple paths through multiple channels between the host and a particular peripheral using the busy vector and queue vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.