Data processor and method for providing show cycles on a fast multiplexed bus
US5548794A · kind A · utility
18Cited by
5References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1994 |
| Grant date | Aug 20, 1996 |
| Priority date | — |
| Expiry date | Dec 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.