Method for producing a PMOS transistor
US5550069A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | May 2, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/965
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a PMOS transistor. A p doped substrate and an n doped trough are provided by implantation and subsequent diffusion. The transistor is insulated by means of a field oxide layer. The transistor gates are produced using a photolithographic pattern. The photoresist left from the photolithographic pattern after the gate is etched is used as the mask of the drain region at the gate-side end for at least one p.sup.- implantation. The thickness of the edge of the photoresist layer decreases towards the surface of the drain region at the gate edge. Due to this decreasing thickness, when the implant is introduced the flank (17, 19) of the implantation concentration profile (16, 18) is deflected towards the channel below the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.