Semiconductor memory device and defective memory cell correction circuit
US5550394A · kind A · utility
29Cited by
4References
6Claims
0Family size
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Key dates
| Filing date | Jun 18, 1993 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jun 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.