Single delay line adjustable duty cycle clock generator
US5550499A · kind A · utility
37Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Apr 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.