Memory cache with low power consumption and method of operation
US5550774A · kind A · utility
14Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Sep 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.