Digital phase alignment and integrated multichannel transceiver employing same
US5550860A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Apr 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.