Memory cache with automatic alliased entry invalidation and method of operation
US5550995A · kind A · utility
14Cited by
3References
18Claims
0Family size
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Inventors
Key dates
| Filing date | Jan 3, 1994 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jan 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and waits until the data is requested again before it invalidates any cache aliased entries in the semi-associative cache array. This invalidation step requires no dedicated cycle but instead is a result of the memory cache being able to simultaneously read from the semi-associative cache array and the cache reload buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.