Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU
US5551010A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1992 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Nov 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory accessing device is coupled to a first bus which connects a first buffer storage unit in a central processing unit to a second buffer storage unit. The memory accessing device can access, through the first bus, at least one of the first buffer storage unit and the second buffer storage unit independently of the central processing unit. The memory accessing device includes an address generating circuit for generating an address to access either or both of the first buffer storage unit and the second buffer storage unit. An output control unit in the memory accessing device outputs the address generated by the address generating circuit to the first bus. An output of the control unit enter an idle state if the second buffer storage unit issues a request for access to the first buffer storage unit when the memory accessing device obtains a right to use the first bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.