Method and apparatus for designing integrated circuits according to master slice approach
US5551014A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 1, 1995 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Mar 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAD system designs mask patterns for use in a master slice integrated circuit processing. The system includes an input device such as a mouse interface, and a display unit for symbolically displaying circuit elements and cells. A first data base stores a net list of circuit design information. A second data base stores data relating to the structure of a master slice bulk and various types of elemental cells formed in the master slice. A processing unit of the CAD system causes the display unit to display both a circuit design scheme and the master slice bulk on a screen of the display unit. The processing unit produces data about the initial positions of a pair of contact hole patterns by which a resistor is defined in a resistive cell region of the master slice, and automatically shifts the contact hole patterns from the initial positions to another position, in order to avoid interference between a wiring pattern on the master slice bulk and the contact hole patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.