Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
US5551033A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1992 |
| Grant date | Aug 27, 1996 |
| Priority date | — |
| Expiry date | Jun 4, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.