Multi-voltage-lever master-slice integrated circuit
US5552618A · kind A · utility
14Cited by
10References
1Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 19, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Oct 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05554
Abstract
A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.