Output buffer circuit having gate voltage control circuit of gate current controlling transistor connected to output transistor
US5552719A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The output buffer circuit according to the present invention comprises: a P-channel type output transistor which is provided between a first power supply terminal and an output terminal and receives an input signal at a gate thereof; an N-channel type transistor which is provided between the output terminal and a second power supply and has a gate connected to a drain of a gate current controlling transistor; a circuit for supplying the input signal to a source of the gate current controlling transistor; and a voltage control generation circuit which generates as a gate voltage of the gate current controlling transistor a first voltage value which is smaller than a value of the power supply voltage for a predetermined time, and further generates a second voltage value which is higher than the first voltage value after the elapse of the predetermined time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.