High resolution digital phase locked loop with automatic recovery logic
US5552726A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1993 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | May 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit 11 includes a phase detection circuit 12, a means for phase adjustment, and a recovery circuit 18. The phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means. The phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals. The recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means. The phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means. The circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.