Zero phase start optimization using mean squared error in a PRML recording channel
US5552942A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Aug 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.