Three phase inverter circuit with improved transition from SVPWM to six step operation
US5552977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Jun 20, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/53875
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
When negative times are calculated for zero space vectors of a SVPWM controlled three phase inverter circuit, the zero vector times are set to zero, the non-zero space vector closer to a commanded space vector is preserved, and the non-zero space vector farther from the commanded space vector is truncated. Thus, control of the inverter circuit seamlessly transits from SVPWM to full six step operation. In one arrangement, for each negative calculated zero space vector time, the larger of the non-zero space vector times is set to the minimum of its calculated time and the pulse width modulation control period (TPWM), and the smaller of the calculated non-zero space vector times is set equal to TPWM less the set value of the larger of the non-zero space vector times. In another arrangement, each negative calculated zero space vector time is algebraically combined with the smaller of the non-zero space vector times. If the resulting non-zero space vector time is greater than or equal to zero, it is used together with the calculated time for the larger of the non-zero space vectors. If the resulting non-zero space vector time is less than zero, the time for the larger of the non-zero sp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.