Method and system using the design pattern of IC chips in the processing thereof
US5552996A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Feb 16, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/941
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
The techniques of the present invention facilitate the control of an IC chip fabrication level of a fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.