Fully digital data separator and frequency multiplier
US5553100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Apr 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.