Device for controlling data transfer between chips via a bus
US5553252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Aug 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/127
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A draw control chip and video chips V1-V4 are provided. They are connected by a 64-bit data bus, a 4-bit program signal line, and a 1-bit ready signal line. The video chip V1 comprises a decoder DEC1, a program buffer address register PBAR, a sequencer SEQ, a program buffer PB, a decoder DEC2, an address control unit, a selector SEL, and various registers. The video chip V1 and the video buffer APA1 are connected by the data bus. This system is used to transfer data from the control chip to the various video chips in a single operation. The 64-bit data bus can be divided into smaller sections allowing smaller segments of data to be simultaneously processed by the video chips. Additionally, the video chips are capable of providing data directly to one another without accessing the control chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.