Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers
US5553259A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1995 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Oct 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and implementation is supplied for the synchronous loading and integrity checking of registers located in two different integrated circuit chips. Thus in a computer system having cache memory where the cache memory is sliced into two portions, one of which holds even addresses and the other of which holds odd addresses, there is provided two individual chips each of which has a program word address register which is loaded at the exact same period of time and which is additionally incremented in both cases at the exact same period of time. Further means are provided for checking the integrity of the program word address registers in the first slice and the second slice of the cache in order to insure that they are coherent, or if not coherent, then a disable signal will prevent usage of the address data involved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.