Method and apparatus for efficient cache refilling by the use of forced cache misses
US5553264A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1994 |
| Grant date | Sep 3, 1996 |
| Priority date | — |
| Expiry date | Jun 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention, one of the bits in the tag value in the cache is hard-wired, for example, to 0, at such a position in the cache that that bit is always set to 0 when a tag is stored in the cache (or forced to 0 when a tag is read from the cache). Instructions executed by the processor can specify a read outside the cache, i.e. of the most recent data written to the main memory by some DMA agent, by specifying a read address with the designated bit equal to one. In this way, a cache miss is forced, allowing the processor to read the most recent data from the main memory of the system and to cache the data. As the cache is refilled from the main memory, the hard-wired tag bit of course remains set to zero. So later processor instructions that read data within the same cache refill block would use the normal address of that data (having the designated bit set to zero). These subsequent reads will not force a cache miss. Instructions executed by the processor can flush the cache by reading a sequence of addresses in which the designated tag bit is one. Since the designated bit is 0 in all cache tags, there will be misses on all words, so the entire cache will be filled from t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.