Process for fabricating two loads having different resistance levels in a common layer of polysilicon
US5554554A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Feb 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. In accordance with the method, a layer of polysilicon having a first resistance level is formed on a semiconductor circuit structure. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.