Nonvolatile semiconductor memory device having a memory cell transistor and a select transistor
US5554867A · kind A · utility
29Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Dec 9, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device is provided including a DINOR (Divided Bit Line NOR) type cell that allows further reduction of the cell size while ensuring immunity from drain-disturb. In the nonvolatile semiconductor memory device, a sub-bit line is formed to have a length corresponding to the length of 16-1024 memory cell transistors. Memory cell transistors corresponding to the length of that sub-bit line are connected to the sub-bit line. Thus, the effective cell size is reduced while ensuring immunity from drain-disturb.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.