Six-transistor cell with wide bit-line pitch, double words lines, and bit-line contact shared among four cells
US5554874A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM memory is arranged into groups of four cells sharing a single active region with a contact to one of the bit lines. The shared active region forms the sources of four access transistors. The group of four cells requires only one pair of bit lines instead of the usual two pairs of bit lines. Thus a pair of bit lines occurs for every two cells rather than for every cell. This increases the bit-line pitch and facilitates design and layout of the sense amps. Since only one of the four cells can drive the bit lines at any time, four word lines are used instead of only two. Each cell has two word lines crossing over it, and the cells in a row alternately connect to one or the other word line. Since word-line drivers and decoders are simpler and easier to lay out than the sense amps, the tighter word-line pitch is acceptable. An unused metal line occurs for every two columns of cells. The bit lines are shielded from this unused metal line by power and ground lines. Thus the shielded metal line is ideal for system interconnect through the RAM when the RAM is embedded in a larger system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.