Circuit arrangement for delaying a functional signal
US5554949A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1993 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Dec 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/81
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output. The the input circuit of a storage device being activatable, together with the output circuit of the next storage device in the row, by a respective activation device, which includes a shift register device formed by a chain of bistable trigger circuits in which the output of each of the trigger circuits is connected to the input of the next trigger circuit in the chain, each activation device including one of the trigger circuits and all trigger circuits being switched by the clock signal, and also comprising a command device which applies a (first) start pulse to the first trigger circuit in the shift register device at a first instant and which enables the shift register device to propagate the start pulse through the chain of trigger circuits in conformity with the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.