Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US5555381A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.