Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
US5555384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Oct 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability. At the effective end of the pipeline, the Controller monitors all instructions in the pipeline, notes all potential resource conflicts, and resolves these potential conflicts by either the insertion of an appropriate number of HOLD states or the conclusion that no actual resource competition exists.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.