Hierarchical queuing in a system architecture for improved message passing and process synchronization
US5555396A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Dec 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.