Extended Harvard architecture computer memory system with programmable variable address increment
US5555424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Oct 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extended Harvard architecture memory system which features an address store for containing an ordered sequence of program memory addresses, and a value store for containing a series of related data value sets. Each of the addresses contained in the address store is associated with a distinct set of instructions, such as a subroutine, that is contained in the program memory. The address store may also contain the address of one or more instruction arguments that are, in turn, contained in the value store or in a separate data memory. Both the address store and the value store are preferably connected to the same data communication path which is used by the data memory of the computer. The value store also includes a logic interface for enabling a plurality of different address increments to be programmably selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.