Data processing system having a compensation circuit for compensating for capacitive coupling on a bus
US5555513A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1994 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Jul 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compensation circuit (64) for ensuring that a first conductor (60) of a plurality of parallel conductors (60, 61, 62) in a bus (50) remains at a logic high voltage when a second conductor (61) adjacent to the first conductor (60) transitions from a logic high voltage to a logic low voltage. The compensation circuit (64) senses when the voltage on the second conductor (61) is reduced from a logic high voltage to a logic low voltage, and causes the first conductor (60) to be coupled to a power supply voltage terminal to prevent a logic high voltage on the first conductor (60) from being reduced toward a logic low voltage due to a capacitive coupling between the first conductor (60) and the second conductor (61).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.