Apparatus and method for efficient carry skip incrementation
US5555517A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Jan 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5055
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.