Semi-synchronous dual port FIFO
US5555524A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FIFO is provided which has two synchronous ports that may operate asynchronously to one another. The FIFO design is unaffected by gate delays, and is therefore especially useful in an integrated circuit where gate delays may not be easily controlled (such as a standard cell or gate array design.) In the FIFO, a write counter controlled by a write clock outputs a write address and a read counter controlled by a read clock with a different frequency outputs a read address. Synchronization circuits are provided to synchronize the read address to the write clock and the write address to the read clock. The synchronized read and write addresses are used to generate full and empty indicators for the FIFO and an occupancy level for the FIFO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.