Dynamic random access memory persistent page implemented as processor register sets
US5555528A · kind A · utility
2Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1995 |
| Grant date | Sep 10, 1996 |
| Priority date | — |
| Expiry date | May 25, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.