Flash EEPROM and EPROM arrays with select transistors within the bit line pitch
US5557124A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Mar 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed. The isolating oxide elements are located under every odd column in the upper area, under each column in the middle area, under each odd column in one row of the lower area and under each even column in the other row of the lower area. Bit line select and erase select rows are in the upper and middle areas, respectively, and two column select rows are in the lower area. Erase select transistors are …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.