Apparatus and method for generating a phase-controlled clock signal
US5557224A · kind A · utility
53Cited by
21References
30Claims
0Family size
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Key dates
| Filing date | Apr 15, 1994 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Apr 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.