Differential amplifier with mismatch correction using floating gates
US5557234A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 1995 |
| Grant date | Sep 17, 1996 |
| Priority date | — |
| Expiry date | Mar 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45661
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Differential amplifier (10) incorporates five metal oxide field effect transistors (MOSFETs) (M1 to M5). The transistors (M1 to M5) are a source-coupled pair of input transistors (M1, M2) with sources connected to a current control transistor (M5) and having respective drain load transistors (M3, M4). The transistors (M1 to M5) have floating gates (F1 to F5) and input gates (G1 to G5). The amplifier (10) is adjusted to counteract differing input transistor threshold voltage by charging one of the input transistor floating gates (G1 , G2) to reduce amplifier offset voltage extrapolated to zero input transistor drain current. It is then adjusted to reduce discrepancies between actual and design values of input transistor drain voltage by charging one or both of the drain load transistor floating gates (F3, F4). The amplifier may be arranged as an operational amplifier (20) with a second state (16) connected to an input transistor drain. The operational amplifier input offset voltage is determined by comparing the second stage output with a reference and feeding a resulting differences signal to the amplifier input. The input offset voltage is then counteracted by charging an input tr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.